A fabrication of a master slice semiconductor integrated circuit, such as a gate array or an embedded array, has usually two phases which are called a pre design phase and a post design phase. In a pre design phase, a large number of transistors are fabricated ahead of design completion. And, in a post design phase, transistors are interconnected using metal wires which allow the semiconductor devices to meet each customer's specific requirements after design completion. In a master slice semiconductor integrated circuit, transistors are regularly arranged in a number of unit groups called basic cells each having several transistors.
Miniaturization of wiring has been made progress faster than miniaturization of a transistor in Deep submicron LSI in recent years. It is difficult thereby, to connect a wiring in a basic cell to external wiring freely in a master slice semiconductor integrated circuit.
Japanese Patent Laid Open No. H8-51194 describes a semiconductor integrated circuit using the first layer metal wiring on a field of a basic cell for connection with external wiring, or preparing the first layer via contact in a place distant from a contact in a transistor of a basic cell.
However, such a semiconductor integrated circuit has a problem that there is limit to position of terminals being used for connection to external wirings in a basic cell. Also there is a problem that compaction of a basic cell is difficult.
Japanese Patent Laid Open No. H8-18021 describes a master slice semiconductor integrated circuit arranging a low threshold voltage cell array adjoining a high threshold voltage cell array for low voltage operation. And, Japanese Patent Laid Open No. H6-188397 describes a master slice semiconductor integrated circuit preparing a special cell array which constitutes sequential circuits, such as flip flops, to prevent a clock skew problem.
These approaches have a problem that a placement position of a cell array for low threshold voltage or sequential circuits was being fixed.